View M40SZ100WMQ6F_8283639.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is information on a product in full production. december 2013 docid007528 rev 4 1/20 m40sz100w 3 v nvram supervisor for lpsram datasheet - production data features ? convert low power srams into nvrams ? 3 v operating voltage ? precision power monitoring and power switching circuitry ? automatic write-protection when v cc is out-of- tolerance ? choice of supply voltage and power-fail deselect voltage: ?v cc = 2.7 to 3.6 v; 2.55 v ? v pfd ? 2.70 v ? reset output ( rst) for power on reset ? 1.25 v reference (for pfi/ pfo) ? less than 15 ns chip enable access propagation delay ? battery low pin ( bl) ? rohs compliant ? lead-free second level interconnect description the m40sz100w nvram controller is a self- contained device which converts a standard low- power sram into a non-volatile memory. a precision voltage reference and comparator monitors the v cc input for an out-of-tolerance condition. when an invalid v cc condition occurs, the conditioned chip enable output ( e con) is forced inactive to write protect the stored data in the sram. during a power failure, the sram is switched from the v cc pin to the external battery to provide the energy required for data retention. on a subsequent power-up, the sram remains write-protected until a valid power condition returns. 16 1 so16 www.st.com
contents m40sz100w 2/20 docid007528 rev 4 contents 1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 data retention lifetime calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 power-on reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 reset input (rstin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 battery low pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 v cc noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
docid007528 rev 4 3/20 m40sz100w list of tables 20 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. power-down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. reset ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. dc and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. so16 ? 16-lead plastic small outline package mechanical data. . . . . . . . . . . . . . . . . . . . . 17 table 9. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 10. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
list of figures m40sz100w 4/20 docid007528 rev 4 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. power-down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. rstin timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. ac testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10. ac testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 11. so16 ? 16-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
docid007528 rev 4 5/20 m40sz100w device overview 20 1 device overview figure 1. logic diagram table 1. signal names e chip enable input e con conditioned chip enable output rst reset output (open drain) rstin reset input bl battery low output (open drain) v out supply voltage output v cc supply voltage v bat backup supply voltage pfi power fail input pfo power fail output v ss ground nc not connected internally ai03933 v cc m40sz100w bl v ss e v out pfi e con pfo rst rstin v bat
device overview m40sz100w 6/20 docid007528 rev 4 figure 2. pin connections figure 3. block diagram 1. open drain output ai03935 8 2 3 4 5 6 710 16 15 14 13 12 11 1 rst e con v ss nc nc v cc m40sz100w pfo v bat 9 nc rstin bl nc pfi nc v out e ai04766 compare v pfd = 2.65 v v cc compare v so = 2.5v v out v bl = 2.5v bl (1) compare 1.25v pfi pfo por v bat compare e rstin e con rst (1)
docid007528 rev 4 7/20 m40sz100w device overview 20 figure 4. hardware hookup ai04767 v cc e e con v ss v out v cc 1mb or 4mb lpsram 3.0v, 3.3v pfi 0.1 f 0.1 f m40sz100w e pfo rst bl to microprocessor reset to battery monitor circuit unregulated voltage regulator v cc v in r1 r2 from microprocessor rstin v bat to microprocessor nmi
operation m40sz100w 8/20 docid007528 rev 4 2 operation the m40sz100w, as shown in figure 4 on page 7 , can control one (two, if placed in parallel) standard low-power sram. this sram must be configured to have the chip enable input disable all other input signals. most slow, low-power srams are configured like this, however many fast srams are not. during normal operating conditions, the conditioned chip enable ( e con ) output pin follows the chip enable ( e) input pin with timing shown in table 2 on page 10 . an internal switch connects v cc to v out . this switch has a voltage drop of less than 0.3 v (i out1 ). when v cc degrades during a power failure, e con is forced inactive independent of e. in this situation, the sram is unconditionally write protected as v cc falls below an out-of- tolerance threshold (v pfd ). for the m40sz100w the power fail detection value associated with v pfd is shown in table 7 on page 16 . if chip enable access is in progress during a power fail detection, that memory cycle continues to completion before the memory is write protected. if the memory cycle is not terminated within time t wpt , e con is unconditionally driven high, write protecting the sram. a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the sram's contents. at voltages below v pfd (min), the user can be assured the memory will be write protected within the write protect time (t wpt ) provided the v cc fall time does not exceed t f (see table 2 on page 10 ). as v cc continues to degrade, the internal switch disconnects v cc and connects the internal battery to v out . this occurs at the switchover voltage (v so ). below the v so , the battery provides a voltage v ohb to the sram and can supply current i out2 (see table 7 on page 16 ). when v cc rises above v so , v out is switched back to the supply voltage. output e con is held inactive for t cer (120 ms maximum) after the power supply has reached v pfd , independent of the e input, to allow for processor stabilization (see figure 6 on page 10 ). 2.1 data retention lifetime calculation most low power srams on the market today can be used with the m40sz100w nvram controller. there are, however some criteria which should be used in making the final choice of which sram to use. the sram must be designed in a way where the chip enable input disables all other inputs to the sram. this allows inputs to the m40sz100w and srams to be ?don't care? once v cc falls below v pfd (min) (see figure 5 on page 9 ). the sram should also guarantee data retention down to v cc = 2.0 v. the chip enable access time must be sufficient to meet the system needs with the chip enable propagation delays included. if data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular srams being evaluated. most srams specify a data retention current at 3.0 v. manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). the system level requirements will determine the choice of which value to use. the data retention current value of the srams can then be added to the i ccdr value of the m40sz100w to determine the total current requirements for data retention. caution: take care to avoid inadvertent discharge through v out and e con after battery has been attached.
docid007528 rev 4 9/20 m40sz100w operation 20 for a further more detailed review of lifetime calculations, please see application note an1012. figure 5. power-down timing ai03936 v cc e e con tf tfb v ohb v pfd (max) v pfd (min) v so twpt v pfd rst pfo valid
operation m40sz100w 10/20 docid007528 rev 4 figure 6. power-up timing table 2. power-down/up ac characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 2.7 to 3.6 v (except where noted). min max unit t f (2) 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200 s after v cc passes v pfd (min). v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. v pfd (min) to v ss v cc fall time 10 s t pfd pfi to pfo propagation delay 15 25 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t epd chip enable propagation delay (low or high) 15 ns t rb v ss to v pfd (min) v cc rise time 1 s t cer chip enable recovery 40 120 ms t rec v pfd (max) to rst high 40 200 ms t wpt write protect time 40 200 s ai03937 v cc e e con tr tcer v ohb v pfd (max) v pfd (min) v so v pfd tepd tepd rst trec trb valid pfo
docid007528 rev 4 11/20 m40sz100w operation 20 2.2 power-on reset output all microprocessors have a reset input which forces them to a known state when starting. the m40sz100w has a reset output ( rst) pin which is guaranteed to be low by v pfd (see table 7 on page 16 ). this signal is an open drain configuration. an appropriate pull-up resistor to v cc should be chosen to control the rise time. this signal will be valid for all voltage conditions, even when v cc equals v ss (with valid battery voltage). once v cc exceeds the power failure detect voltage v pfd , an internal timer keeps rst low for t rec to allow the power supply to stabilize. 2.3 reset input ( rstin) the m40sz100w provides one independent input which can generate an output reset. the duration and function of this reset is identical to a reset generated by a power cycle. table 3 and figure 7 illustrate the ac reset characteristics of this function. pulses shorter than t rlrh will not generate a reset condition. rstin is internally pulled up to v cc through a 100 k ? resistor. figure 7. rstin timing waveform 1. with pull-up resistor table 3. reset ac characteristics 2.4 battery low pin the m40sz100w automatically performs battery voltage monitoring upon power-up, and at factory-programmed time intervals of at least 24 hours. the battery low ( bl) pin will be asserted if the battery voltage is found to be less than approximately 2.5 v. the bl pin will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. symbol parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 2.7 to 3.6 v (except where noted). min max unit t rlrh (2) 2. pulse width less than 50 ns will result in no reset (for noise immunity). rstin low to rstin high 200 ns t r1hrh (3) 3. c l = 50 pf (see figure 9 on page 15 ). rstin high to rst high 40 200 ms ai04768 rst (1) rstin trlrh tr1hrh
operation m40sz100w 12/20 docid007528 rev 4 if a battery low is generated during a power-up sequence, this indicates that the battery is below 2.5 v and may not be able to maintain data integrity in the sram. data should be considered suspect, and verified as correct. a fresh battery should be installed. if a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. however, data is not compromised due to the fact that a nominal v cc is supplied. in order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. the m40sz100w only monitors the battery when a nominal v cc is applied to the device. thus applications which require extensive durations in the battery backup mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. the bl pin is an open drain output and an appropriate pull-up resistor to v cc should be chosen to control the rise time. 2.5 power-fail input/output the power-fail input (pfi) is compared to an internal reference voltage (independent from the v pfd comparator). if pfi is less than the power-fail threshold (v pfi ), the power-fail output ( pfo) will go low. this function is intended for use as an undervoltage detector to signal a failing power supply. typically pfi is connected through an external voltage divider (see figure 4 on page 7 ) to either the unregulated dc input (if it is available) or the regulated output of the v cc regulator. the voltage divider can be set up such that the voltage at pfi falls below v pfi several milliseconds before the regulated v cc input to the m40sz100w or the microprocessor drops below the minimum operating voltage. during battery backup, the power-fail comparator turns off and pfo goes (or remains) low. this occurs after v cc drops below v pfd (min). when power returns, pfo is forced high, irrespective of v pfi for the write protect time (t rec ), which is the time from v pfd (max) until the inputs are recognized. at the end of this time, the power-fail comparator is enabled and pfo follows pfi. if the comparator is unused, pfi should be connected to v ss and pfo left unconnected. 2.6 v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store energy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic bypass capacitor value of 0.1 f (as shown in figure 8 on page 13 ) is recommended in order to provide the needed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate negative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, stmicroelectronics recommends connecting a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount.
docid007528 rev 4 13/20 m40sz100w operation 20 figure 8. supply voltage protection ai00622 v cc 0.1f device v cc v ss
maximum ratings m40sz100w 14/20 docid007528 rev 4 3 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4. absolute maximum ratings caution: negative undershoots below ?0.3 v are not allowed on any pin while in the battery backup mode. symbol parameter value unit t stg storage temperature (v cc off) ?55 to 125 c t sld (1) 1. for so package, lead-free (pb-free) lead finish: reflow at peak temperature of 260 c (the time above 255 c must not exceed 30 seconds). lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.3 to v cc +0.3 v v cc supply voltage ?0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w
docid007528 rev 4 15/20 m40sz100w dc and ac parameters 20 4 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in table 5: dc and ac measurement conditions . designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. table 5. dc and ac measurement conditions figure 9. ac testing load circuit figure 10. ac testing input/output waveforms table 6. capacitance parameter value v cc supply voltage 2.7 to 3.6 v ambient operating temperature ?40 to 85 c load capacitance (c l ) 50 pf input rise and fall times ? 5 ns input pulse voltages 0.2 to 0.8v cc input and output timing ref. voltages 0.3 to 0.7v cc symbol parameter (1)(2) 1. sampled only, not 100% tested. 2. at 25 c, f = 1 mhz. min max unit c in input capacitance - 7 pf c out (3) 3. outputs deselected. output capacitance - 10 pf ai02393 c l = 50pf c l includes jig capacitance 333 ? device under test 1.73v ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc
dc and ac parameters m40sz100w 16/20 docid007528 rev 4 table 7. dc characteristics sym parameter test condition (1) 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 2.7 to 3.6 v (except where noted). min typ max unit i cc supply current outputs open 0.5 ma i ccdr data retention mode current (2) 2. measured with v out and e con open. 50 200 na i li (3) 3. rstin internally pulled-up to v cc through 100 k ? resistor. input leakage current 0 v ? v in ? v cc 1 a input leakage current (pfi) ?25 2 25 na i lo (4) 4. outputs deselected. output leakage current 0 v ? v out ? v cc 1 a i out1 (5) 5. external sram must match supervisor chip v cc specification. v out current (active) v out > v cc ? 0.3 100 ma i out2 v out current (battery backup) v out > v bat ? 0.3 100 a v bat battery voltage 2.5 3.0 3.5 (6) v v ih input high voltage 0.7v cc v cc + 0.3 v v il input low voltage ?0.3 0.3v cc v v oh output high voltage (6) 6. for pfo pin (cmos). i oh = ?1.0 ma 2.4 v v ohb v oh battery backup (7) 7. chip enable output ( e con ) can only sustain cmos leakage currents in the battery backup mode. higher leakage currents will reduce battery life. i out2 = ?1.0 a 2.5 2.9 3.5 v v ol output low voltage i ol = 3.0 ma 0.4 v output low voltage (open drain) (8) 8. for rst & bl pins (open drain). i ol = 10 ma 0.4 v v pfd power-fail deselect voltage 2.55 2.60 2.70 v v pfi pfi input threshold v cc = 3 v 1.225 1.250 1.275 v pfi hysteresis pfi rising 20 70 mv v so battery backup switchover voltage 2.5 v
docid007528 rev 4 17/20 m40sz100w package mechanical data 20 5 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 11. so16 ? 16-lead plastic small package outline note: drawing is not to scale. table 8. so16 ? 16-lead plastic small outline package mechanical data so-b e n cp b e a2 d c l a1 h a 1 symbol mm inches typ. min. max. typ. min. max. a 1.75 0.069 a1 0.10 0.25 0.004 0.010 a2 1.60 0.063 b 0.35 0.46 0.014 0.018 c 0.19 0.25 0.007 0.010 d 9.80 10.00 0.386 0.394 e 3.80 4.00 0.150 0.158 e 1.27 ? ? 0.050 ? ? h 5.80 6.20 0.228 0.244 l 0.40 1.27 0.016 0.050 a 08 08 n16 16 cp 0.10 0.004
part numbering m40sz100w 18/20 docid007528 rev 4 6 part numbering table 9. ordering information scheme for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m40sz 100w mq 6 f device type m40sz supply voltage and write protect voltage 100w = v cc = 2.7 to 3.6 v; v pfd = 2.6 to 2.7 v package mq = so16 temperature range 6 = ?40 to 85 c shipping method f = lead-free ecopack ? package, tape & reel
docid007528 rev 4 19/20 m40sz100w revision history 20 7 revision history table 10. document revision history date revision changes dec-2001 1.0 first issue 13-may-2002 1.1 modify reflow time and temperature footnote ( table 4 ) 01-aug-2002 1.2 add marketing status (cover page; table 9 ) 15-sep-2003 1.3 remove reference to m68xxx (obsolete) part ( figure 4 ); update disclaimer 20-nov-2007 2 reformatted document; added lead-free second level interconnect information to cover page and section 5: package mechanical data ; updated table 4 and 9 . 25-oct-2010 3 updated cover page, section 3 , table 9 , ecopack ? text in section 5 ; reformatted document; minor textual changes. 16-dec-2013 4 removed snaphat and soh28 package option as well as 5 v part (m40sz100y) from datasheet removed shipping option in tubes from table 9
m40sz100w 20/20 docid007528 rev 4 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. a ll st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industr y domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of M40SZ100WMQ6F

	To Download M40SZ100WMQ6F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .